Publications & Patents
- Towards reconfigurable acceleration in mobile phones via dynamic compilation. HiPEAC Spring 2013 Computing Systems Week (CSW) part of 1st ACM European Computing Research Congress, May 2-3, 2013. [Slides]
- Aayush Ankit, Izzat El Hajj, Sai Rahul Chalamalasetti, Geoffrey Ndu, Martin Foltin, R. Stanley Williams, Paolo Faraboschi, Wen-mei Hwu, John Paul Strachan, Kaushik Roy, Dejan S Milojicic. PUMA: A Programmable Ultra-efficient Memristor-based Accelerator for Machine Learning Inference. In 2019 Architectural Support for Programming Languages and Operating Systems (ASPLOS ’19), April 13–17, 2019 [Paper]
- Pedro Bruel, Sai Rahul Chalamalasetti, Chris Dalton, Izzat El Hajj, Alfredo Goldman, Catherine Graves, Wen-mei Hwu, Phil Laplante, Dejan Milojicic, Geoffrey Ndu, John Paul Strachan. Generalize or Die: Operating Systems Support for Memristor-based Accelerators. In Proceedings of the 2017 IEEE International Conference on Rebooting Computing (ICRC) 8–9 November 2017 Washington DC, USA. [Paper]
- Reto Achermann, Chris Dalton, Paolo Faraboschi, Moritz Hoffmann, Dejan Milojicic, Geoffrey Ndu, Alexander Richardson, Timothy Roscoe, Adrian L. Shaw, Robert N. M. Watson. Separating Translation from Protection in Address Spaces with Dynamic Remapping. In Proceedings of the 16th Workshop on Hot Topics in Operating Systems (HotOS-XVI), May 7-10, 2017, Whistler, Canada. [Paper]
- G.Ndu, J.Navaridas and M. Lujan. CHO: Towards a Benchmark Suite for OpenCL FPGA Accelerators. In Proceedings of the 3rd International Workshop on OpenCL, May 12-13, 2015, Palo Alto, USA. [Paper][Slides]
- O. Abella, G. Ndu, et al. An Empirical Evaluation of High-level Synthesis Languages and Tools for Database Acceleration. In Proceedings of the 24th International Conference on Field Programmable Logic and Applications (FPL 2014), September 2-4, 2014, Munich, Germany. [Paper][Slides]
- G. Ndu and J. Garside. Boosting single thread performance in mobile processors via reconfigurable acceleration. In Proceedings of the 8th International Symposium on Applied Reconfigurable Computing (ARC 2012), LNCS 7199, pp. 114-127, Hong Kong, China, March 19-23, 2012. [Paper]
- G. Ndu and J. Garside. Architecture for Runtime Hardware Compilation. 5th HiPEAC Workshop on Reconfigurable Computing, Heraklion, Greece, January 2011.
- G. Ndu and J. Garside. An Evaluation of Asynchronous Architecture for System Level Power Reduction.In Proceedings of the Fifth UK Embedded Forum, Leicester, UK, September 2009.
- G. Ndu and J. Garside. A Co-designed Dynamic Compilation Framework for Reconfigurable Processors. Sixteenth International Conference on Architectural Support for Programming Languages and Operating Systems (ASPLOS 2011), Newport Beach, USA March 2011.
- G.Ndu, J.Navaridas and M. Lujan. CHO: A Benchmark Suite for OpenCL-based FPGA Accelerators. University Manchester Technical Report UNIMAN-COMP-APT-TR-02-05-2014. May 2, 2014
- G. Ndu and J. Garside. Architecture for Runtime Hardware Compilation. Tech Report, TR-HiPEAC-0014, HIPEAC, January 2011.
- G. Ndu. Boosting Single Thread Performance in Mobile Processors using Reconfigurable Acceleration. PhD.Thesis, University of Manchester, Manchester, UK 2012. [Thesis]
- G. Ndu. An Evaluation of Asynchronous Architecture for System Level Power Reduction. MSc.Thesis, University of Manchester, Manchester, UK 2008.[Abstract]