Software

CHO: a benchmark suite for OpenCL-based FPGA accelerators.

PostgresCustomScan: offloading PostgreSQL scans to GPUs/FPGAs using OpenCL

Source-Analyzer: a simple clang compiler plugin for source characterizing applications.

Chisel Designer's Library: contains Chisel (is an open-source high-level hardware construction language) versions of the RTL implementations in Verilog Designer's Library book